1. Field
Exemplary embodiments of the present invention relate to a clock transfer circuit, and more particularly, to a semiconductor device including the clock transfer circuit.
2. Description of the Related Art
Generally, synchronous semiconductor devices including semiconductor memory devices performs a data read operation and a data write operation in synchronization with an internal clock that is generated based on an external clock. The examples of the synchronous semiconductor devices include a Single Data Rate (SDR) Synchronous Dynamic Random Access Memory (SDRAM) device, which outputs data at rising edges of a clock signal, and a Double Data Rate (DDR) SDRAM, which outputs data at rising edges and falling edges of a clock signal.
Here, an internal clock may be supplied as a row clock and a column clock. The row clock is supplied to the circuits that perform the operations of generating and delaying signals related to row operations, such as an active operation, a precharge operation, and a refresh operation, in a semiconductor device. The column clock is supplied to the circuits that perform the operations of generating and delaying signals related to column operations, such as a write operation and a read operation, in a semiconductor device.
FIG. 1 is a block diagram of a conventional semiconductor device.
Referring to FIG. 1, the conventional semiconductor device includes a clock transfer unit 110, a row operation circuit 120, and a column operation circuit 130.
The row operation circuit 120 is a circuit that generates and delays signals related to the row operations of the semiconductor device, and the column operation circuit 130 is a circuit that generates and delays signals related to the column operations of the semiconductor device.
The clock transfer unit 110 transfers an external clock OCLK as an internal clock ICLK and supplies the internal clock ICLK to the row operation circuit 120 and the column operation circuit 130. The clock transfer unit 110 may be a typical clock buffer circuit that generates an output clock by buffering an input clock or a typical clock driver circuit that generates an output clock by driving an input clock, i.e., supplying voltages to an output node in response to an input clock.
Referring to FIG. 1, the clock transfer unit 110 supplies the same internal clock ICLK to the row operation circuit 120 and the column operation circuit 130. In short, the internal clock ICLK is supplied as the aforementioned row clock and column clock.
The column operation, however, is performed in a period from a moment when an active command for activating a word line is applied to a moment when a precharge command for precharging a bit line is applied. Therefore, the column operation circuit 130, for example, a circuit that delays a read command, a write command, and a column address, may not use a column clock except such a period from a moment when the active command is applied to a moment when the precharge command is applied. As described above, however, the conventional technology does not control the enabling period of the row clock and the enabling period of the column clock separately. Thus, the column clock is provided to the column operation circuit 130 even in a period when a column operation is not performed, thereby increasing the operation current of the semiconductor device during the column operation and furthermore increasing power consumption of the semiconductor device.